1. Field of the Invention
The invention relates to programmable logic array (PLA) structures generally, and more particularly to high speed structures for PLAs having a large number of inputs and/or minterms.
2. Background
PLAs are combinational two-level AND-OR structures that can be programmed to realize any sum-of-product logic expression. PLAs are widely used in integrated circuits. Complex integrated circuits such as processors and microprocessors often use several large PLAs.
FIG. 1(a) shows a transistor-level schematic of a basic conventional static PLA. A PLA 100 typically has one AND plane 102 and one OR plane 104. AND plane 102 receives input signals 106, performs a logical function on the input signals and generates a number of minterms 108 (i.e., AND plane output signals) that are provided as input signals to an OR plane 104 of PLA 100. OR plane 104 performs a logical function and produces the final logical outputs of PLA 100. The actual number of input signals, minterm signals, and PLA output signals are determined by the overall logical function that PLA 100 is to implement. It can be seen in the example of FIG. 1(a) that the parasitic capacitive loading of OR plane output lines 110 due to the drain junctions of n-channel transistor pull-downs 112 varies according to the number of pull-downs 112. In this example, output line 110a has only one pull-down, output line 110b has two pull-downs and output line 110c is fully programmed with pull-downs and therefore is the most heavily loaded with parasitic junction capacitance.
The logical structure of a typical PLA 150 is shown in FIG. 1(b). Referring to the circuit implementation shown in FIG. 1(b), it can be seen that Buffer.sub.-- 1 152 is coupled between the input signal sources, and the input terminals of an AND plane 154. Buffer.sub.-- 1 152 provides the input signals with the signal strength required to drive AND plane 154. Buffer.sub.-- 2 156 is coupled between AND plane 154 and an OR plane 158, so as to receive the minterm signals and provide the signal strength required to drive OR plane 158. Although neither Buffer.sub.-- 1 152 or Buffer.sub.-- 2 156 perform logical functions, they do increase the delay from the time an input signal is asserted to when the PLA output signals become valid.
While PLAs have been an extremely valuable element for integrated circuit designers, the current trend in processor architecture toward higher frequencies, and correspondingly shorter cycle times, has made it increasingly difficult to design large PLAs.
A typical problem in large PLA is that, for a desired cycle time, the OR plane does not have enough time to evaluate. In the worst case, all minterms may feed into one particular OR plane output line. In this case a substantial delay would be seen in producing the output if the number of minterms is large, e.g., several hundred, because the loading on the output due to junction capacitance becomes prohibitively large.
What is needed is a PLA that can accept a large number of inputs or minterms and without incurring large delays due to parasitic junction capacitance.